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NexGen Nx586 - Producing the Impossible?

The first samples of the NexGen CPU were manufactured by Yamaha. But Hewlet Packard would act as foundry for the large volumes of the production version of the Nx586. The design team tried to integrate all the chips into a single die with HP's process. Unfortunately the initial yield for a test chip was about zero.
Around the same time the layout tape was also sent out to IBM even though IBM used a different manufacturing process. The IBM manufactured chips were also tested and some of them actually worked. Influenced by the fact that HP was getting out of the foundry business, NexGen made a deal with IBM.

IBM's smaller dimension process (compared to HP's) meant that all the chips for the Nx586 could be integrated into a single die. NexGen's engineers stuck the various chip set mask regions onto the die and wired them together. It was crude because not all the die was optimally used but effective, production could be started. The numerics processor was not integrated because the design was not ready yet.

On June 13 1994 Nexgen announced the foundering deal with IBM. The 3.5million transistor Nx586 and the 700.000 transistor Nx587 would be manufactured using IBM's CMOS 5L process. The technology produced 0.5 micron CMOS silicon with 5 layer metal interconnect on 8 inch wafers. IBM would also package the CPU and FPU cores using its own C4 'flip chip' technology. With this deal volume production could be started and shipping date was set for Q4 of that year.

>>>>>>>>>>>>>Plaatje van de Evaluation board<<<<<<<<<<<<<<

The foundry deal wit IBM was negotiated by Atiq Raza who had joined NexGen in 1990. Interesting about this manufacturing deal was that NexGen only paid for working chips. Yield estimates were not great so this would be a very good deal! Unfortunately many chips worked OK, but at very low frequencies and had to be paid and then scrapped.

Around May 1995 NexGen announced a die shrink for its CPU, one month later more details appeared. The die size was reduced about 40% from 192mm2 (13.9mm x 13.9mm) to 118mm2 (10.8mm x 10.9mm) while still using IBM's 0.5 micron CMOS 5L process. This design change made it possible to increase the number of die's per wafer from 112 to 199. The reduction of the die size was partly realized by using the die more effectively and partly by removing some older unused logic.

The last manufacturing change was the move to the smaller IBM 5S 0.44 micron process. This manufacturing process made the new speed grades P120 and P133 possible.

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